Tags
- 3
- 4
- A
- A17
- Abstract machine
- ACPI
- Adapteva
- Adder
- Addressing mode
- Address space
- Address space layout randomization
- Adreno
- Advanced Micro Devices
- Advanced Power Management
- AI accelerator
- Alternating Turing machine
- Alternative
- Alternatives
- AMD
- An
- Analogue electronics
- AnandTech
- Apollo Guidance Computer
- Application-specific integrated circuit
- Arithmetic logic unit
- Arm
- ARM Holdings
- Ars Technica
- Artificial neural network
- Atom Journey
- Attack
- Auxiliary memory
- Barrel shifter
- Baseband processor
- Based on
- Behind
- Binary number
- Bit-level parallelism
- Bit-serial architecture
- Bit slicing
- Boolean circuit
- Branch
- Branch predictor
- Branch target predictor
- Bubble
- Bug
- Bugs
- Burroughs Medium Systems
- Bus
- Cache
- Cache coherence
- Cache hierarchy
- Cache prefetching
- Cache replacement policies
- Call stack
- Cannonlake
- Cellular architecture
- Cellular automaton
- Central processing unit
- Chrome
- Circuit
- Clock rate
- Clock signal
- Code
- Code word
- Cognitive computing
- Combinational logic
- Compiler
- Complex instruction set computing
- Complex programmable logic device
- Computer
- Computer architecture
- Computer data storage
- Computer engineering
- Computer performance
- Concatenation
- Conditional
- Control flow
- Control unit
- Cooperative multitasking
- Coprocessor
- Correlation
- Counter
- Counter machine
- Cppdepend
- CPU
- CPU cache
- CPU multiplier
- Data buffer
- Data dependency
- Data parallelism
- Datapath
- DEC Alpha
- Decision tree
- Delay slot
- Desktop
- Deterministic finite automaton
- Digital electronics
- Digital signal processor
- Distributed computing
- DOI
- Dynamic frequency scaling
- Dynamic voltage scaling
- Electronic circuit
- Embedded system
- Endianness
- Exec Shield
- Execution unit
- Exponential function
- Exynos
- Fabric computing
- False sharing
- Field-programmable gate array
- FIFO
- Finite-state machine
- First generation
- Flip-flop
- Floating-point arithmetic
- Floating-point unit
- Flops
- Gate array
- General-purpose computing on graphics processing units
- Glue logic
- Go 2
- Goldmont
- Google Chrome
- GPU
- Gpu architecture
- Graphics processing unit
- Guide
- Hacker
- Hacker News
- Hardware acceleration
- Hardware register
- Hardware security module
- Harvard architecture
- Hazard
- Heterogeneous computing
- Heterogeneous System Architecture
- Hypercomputation
- Hyper-threading
- HyperTransport
- IA-64
- IBM
- IBM 3090
- IBM System/370
- IBM System/390 ES/9000 Enterprise Systems Architecture ESA family
- Image processor
- Impact
- Impacts
- Implementation
- Indirect branch
- Instruction cycle
- Instruction-level parallelism
- Instruction pipelining
- Instruction set architecture
- Instructions per cycle
- Instructions per second
- Integrated circuit
- Intel
- Intel 8080
- Intel 8086
- Intel Atom
- Intel Core
- Intel Core 2
- Intel core i7
- Intel Wa
- International Standard Book Number
- International Standard Serial Number
- Key encapsulation
- Key encapsulation mechanism
- Layout
- Learning vector quantization
- Linux
- LLVM
- Load–store unit
- Logic gate
- Lucian Blaga University of Sibiu
- Machine code
- Machine learning
- Manycore processor
- Memory address
- Memory address register
- Memory controller
- Memory hierarchy
- Memory-level parallelism
- Memory management unit
- Microarchitecture
- MicroBlaze
- Microcode
- Microcontroller
- Micro-operation
- Microprocessor
- MIMD
- MIPS architecture
- MIPS Technologies
- Mixed-signal integrated circuit
- Mobile processor
- Model of computation
- Motorola 68000 series
- Multi-chip module
- Multi-core processor
- Multilayer perceptron
- Multiplexer
- Multiprocessing
- Multithreading
- Nause
- Network on a chip
- Network processor
- Neural network
- Neuromorphic engineering
- New
- Next
- No instruction set computing
- Non-uniform memory access
- Number
- OpenRISC
- Operand forwarding
- Operating system
- Optimization
- Out-of-order execution
- Outs
- P5
- Parallel computing
- Part 1
- Paul Quinn College
- PCGamesN
- Pentium
- Pentium 4
- Pentium II
- Pentium III
- Pentium M
- Perceptron
- Performance optimization
- Performance per watt
- Piledriver
- Pin grid array
- Position-independent code
- Post-quantum cryptography
- Post–Turing machine
- Power management
- Power management integrated circuit
- Power Management Unit
- PowerPC
- PowerPC G4
- Predicate
- Prediction
- Preemption
- Probabilistic Turing machine
- Process
- Processor
- Processor design
- Processor register
- Program counter
- Project Zero
- Public-key cryptography
- Qualcomm
- Qualcomm Snapdragon
- Quantum circuit
- Quantum computing
- Quantum Gate
- Quantum Turing machine
- R2000
- R3000
- R4000
- R8000
- Random-access machine
- Randomization
- Reduced instruction set computer
- Register file
- Register machine
- Register renaming
- Re-order buffer
- Result
- Return statement
- RISC
- RISC-V
- ROM image
- Rosetta 2
- RSA
- Run time
- Ryzen
- Samsung
- Scratchpad memory
- Second
- Secure cryptoprocessor
- Security
- Semiconductor device fabrication
- Sequential logic
- Set
- Shift register
- Silvermont
- Simd
- Simultaneous multithreading
- Single-core
- Single instruction, multiple threads
- Socket AM4
- Soft microprocessor
- Some
- Space
- SPARC
- SPECTRE
- Speculative execution
- S&P Global
- SPMD
- Stack machine
- Stack register
- Stanford MIPS
- State machine
- Status register
- Stored-program computer
- Stream processing
- Subroutine
- Subsequence
- Supercomputer
- SuperH
- Superscalar processor
- SUPS
- SWAR
- Switch
- System on a chip
- Systems
- Task parallelism
- Tensor processing unit
- The Bash Street Kids
- Thread
- Three-dimensional integrated circuit
- Trade-off
- Transactions per second
- Transistor
- Transistor count
- Translation lookaside buffer
- Trees
- Try
- Turing machine
- Ultra-low-voltage processor
- Understood
- Unicore
- Universal Turing machine
- University of Michigan
- Valgrind
- Vax
- Vector processor
- Very long instruction word
- Virtual memory
- Vision processing unit
- Von Neumann architecture
- Vulnerability
- Wayback Machine
- Weekly
- What
- When
- Why
- Wikipedia
- Write buffer
- X86
- X86-64
- X86 instruction listings
- XOR gate
- Z/Architecture
- Zen
- Zen 2